In the prior art, a flash memory cell stores a charge in a floating gate. The stored charge changes a threshold voltage of the memory cell. In a read operation, a read voltage is applied to the gate terminal of the memory cell, and the corresponding indication about whether the memory cell turns on (e.g., a drain current) indicates the programming state of the memory cell. For instance, a memory cell that conducts current during the read operation may have a digital value of “1” assigned; and a memory cell that does not conduct current during the read operation may have a digital value of “0” assigned. A charge may be added to or removed from the floating gate to correspondingly program or erase the memory cell (e.g., to change the memory cell value from “1” to “0”).
Another type of memory cell employs a charge-trapping structure rather than a conductive gate material employed in the floating gate devices. The memory cell includes a charge-trapping layer. When the charge-trapping layer is programmed, a charge may be trapped in the charge-trapping layer, so that the charge does not move through the non-conductive charge-trapping layer. The charge may therefore be retained by the charge-trapping layer until the memory cell is erased, thereby retaining the data state without requiring a continuous source of electrical power to be applied. The charge-trapping memory cell can be operated as a two-sided cell. In other words, because the charge does not move through the non-conductive charge trapping layer, the charge can be localized on different charge-trapping sites. Therefore, a charge-trapping memory cell serving as a multi-bit cell (MBC) or a multi-level cell (MLC) can be created, which can increase the amount of data that can be stored in a memory device without consuming more space.
An MLC has a first bit site and a second bit site for saving two bits of data, wherein each of the first and the second bit sites can store a bit of data. A selected one of the first and the second bit sites has a neighbor bit site. The electric charge of the neighbor bit site can affect the selected bit site. In other words, if the first bit site is previously programmed in a state of a high threshold voltage, the speed of programming the second bit site will be slowed down; i.e. there is a neighbor bit disturb (or a program disturb) when programming the second bit site. There are numerous mechanisms that have been developed in an effort to consider the neighbor bit disturb and the program performance. Some of these mechanisms involve the application of different voltages to the source lines, the bit lines or the word lines. Thus, it may be desirable to provide an improved mechanism for programming a multi-level cell.